/* +---------------+---------------+---------------+ * | Clock: | Control: | Data: | * +---------------+---------------+---------------+ * | SDCLK -> PG8 | SDCAS -> PG15 | D0 -> PD14 | * | SDCKE -> PC3 | SDRAS -> PF11 | D1 -> PD15 | * | | SDCS -> PH3 | D2 -> PD0 | * | | SDWE -> PH5 | D3 -> PD1 | * +---------------+---------------+ D4 -> PE7 | * | Address & Banks: | D5 -> PE8 | * +---------------+---------------+ D6 -> PE9 | * | A0 -> PF0 | A7 -> PF13 | D7 -> PE10 | * | A1 -> PF1 | A8 -> PF14 | D8 -> PE11 | * | A2 -> PF2 | A9 -> PF15 | D9 -> PE12 | * | A3 -> PF3 | A10 -> PG0 | D10 -> PE13 | * | A4 -> PF4 | A11 -> PG1 | D11 -> PE14 | * | A5 -> PF5 | BA0 -> PG4 | D12 -> PE15 | * | A6 -> PF12 | BA1 -> PG5 | D13 -> PD8 | * +---------------+---------------+ D14 -> PD9 | * | | D15 -> PD10 | * +-------------------------------+---------------+ */ static inline void pin_init() { /* Enable clock for GPIO ports */ RCC -> AHB1ENR |= RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; /* Configure GPIO ports */ /* PC3: AF PP + VHS + AF12 */ GPIOC -> MODER |= GPIO_MODER_MODER3_1; GPIOC -> OSPEEDR |= GPIO_OSPEEDER_OSPEEDR3_1 | GPIO_OSPEEDER_OSPEEDR3_0; GPIOC -> AFR[0] |= GPIO_AFRL_AFRL3_3 | GPIO_AFRL_AFRL3_2; /* PD0, PD1, PD8, PD9, PD10, PD14, PD15: AF PP + VHS + AF12 */ GPIOD -> MODER |= GPIO_MODER_MODER15_1 | GPIO_MODER_MODER14_1 | GPIO_MODER_MODER10_1 | GPIO_MODER_MODER9_1 | GPIO_MODER_MODER8_1 | GPIO_MODER_MODER1_1 | GPIO_MODER_MODER0_1; GPIOD -> OSPEEDR |= GPIO_OSPEEDER_OSPEEDR15_1 | GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR14_1 | GPIO_OSPEEDER_OSPEEDR14_0 | GPIO_OSPEEDER_OSPEEDR10_1 | GPIO_OSPEEDER_OSPEEDR10_0 | GPIO_OSPEEDER_OSPEEDR9_1 | GPIO_OSPEEDER_OSPEEDR9_0 | GPIO_OSPEEDER_OSPEEDR8_1 | GPIO_OSPEEDER_OSPEEDR8_0 | GPIO_OSPEEDER_OSPEEDR1_1 | GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR0_1 | GPIO_OSPEEDER_OSPEEDR0_0; GPIOD -> AFR[0] |= GPIO_AFRL_AFRL1_3 | GPIO_AFRL_AFRL1_2 | GPIO_AFRL_AFRL0_3 | GPIO_AFRL_AFRL0_2; GPIOD -> AFR[1] |= GPIO_AFRH_AFRH7_3 | GPIO_AFRH_AFRH7_2 | GPIO_AFRH_AFRH6_3 | GPIO_AFRH_AFRH6_2 | GPIO_AFRH_AFRH2_3 | GPIO_AFRH_AFRH2_2 | GPIO_AFRH_AFRH1_3 | GPIO_AFRH_AFRH1_2 | GPIO_AFRH_AFRH0_3 | GPIO_AFRH_AFRH0_2; /* PE0. PE1, PE7 - PE15: AF PP + VHS + AF12 */ GPIOE -> MODER |= GPIO_MODER_MODER15_1 | GPIO_MODER_MODER14_1 | GPIO_MODER_MODER13_1 | GPIO_MODER_MODER12_1 | GPIO_MODER_MODER11_1 | GPIO_MODER_MODER10_1 | GPIO_MODER_MODER9_1 | GPIO_MODER_MODER8_1 | GPIO_MODER_MODER7_1 | GPIO_MODER_MODER1_1 | GPIO_MODER_MODER0_1; GPIOE -> OSPEEDR |= GPIO_OSPEEDER_OSPEEDR15_1 | GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR14_1 | GPIO_OSPEEDER_OSPEEDR14_0 | GPIO_OSPEEDER_OSPEEDR13_1 | GPIO_OSPEEDER_OSPEEDR13_0 | GPIO_OSPEEDER_OSPEEDR12_1 | GPIO_OSPEEDER_OSPEEDR12_0 | GPIO_OSPEEDER_OSPEEDR11_1 | GPIO_OSPEEDER_OSPEEDR11_0 | GPIO_OSPEEDER_OSPEEDR10_1 | GPIO_OSPEEDER_OSPEEDR10_0 | GPIO_OSPEEDER_OSPEEDR9_1 | GPIO_OSPEEDER_OSPEEDR9_0 | GPIO_OSPEEDER_OSPEEDR8_1 | GPIO_OSPEEDER_OSPEEDR8_0 | GPIO_OSPEEDER_OSPEEDR7_1 | GPIO_OSPEEDER_OSPEEDR7_0 | GPIO_OSPEEDER_OSPEEDR1_1 | GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR0_1 | GPIO_OSPEEDER_OSPEEDR0_0; GPIOE -> AFR[0] |= GPIO_AFRL_AFRL7_3 | GPIO_AFRL_AFRL7_2 | GPIO_AFRL_AFRL1_3 | GPIO_AFRL_AFRL1_2 | GPIO_AFRL_AFRL0_3 | GPIO_AFRL_AFRL0_2; GPIOE -> AFR[1] |= GPIO_AFRH_AFRH7_3 | GPIO_AFRH_AFRH7_2 | GPIO_AFRH_AFRH6_3 | GPIO_AFRH_AFRH6_2 | GPIO_AFRH_AFRH5_3 | GPIO_AFRH_AFRH5_2 | GPIO_AFRH_AFRH4_3 | GPIO_AFRH_AFRH4_2 | GPIO_AFRH_AFRH3_3 | GPIO_AFRH_AFRH3_2 | GPIO_AFRH_AFRH2_3 | GPIO_AFRH_AFRH2_2 | GPIO_AFRH_AFRH1_3 | GPIO_AFRH_AFRH1_2 | GPIO_AFRH_AFRH0_3 | GPIO_AFRH_AFRH0_2; /* PF0 - PF5, PF11 - PF15: AF PP + VHS + AF12 */ GPIOF -> MODER |= GPIO_MODER_MODER15_1 | GPIO_MODER_MODER14_1 | GPIO_MODER_MODER13_1 | GPIO_MODER_MODER12_1 | GPIO_MODER_MODER11_1 | GPIO_MODER_MODER5_1 | GPIO_MODER_MODER4_1 | GPIO_MODER_MODER3_1 | GPIO_MODER_MODER2_1 | GPIO_MODER_MODER1_1 | GPIO_MODER_MODER0_1; GPIOF -> OSPEEDR |= GPIO_OSPEEDER_OSPEEDR15_1 | GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR14_1 | GPIO_OSPEEDER_OSPEEDR14_0 | GPIO_OSPEEDER_OSPEEDR13_1 | GPIO_OSPEEDER_OSPEEDR13_0 | GPIO_OSPEEDER_OSPEEDR12_1 | GPIO_OSPEEDER_OSPEEDR12_0 | GPIO_OSPEEDER_OSPEEDR11_1 | GPIO_OSPEEDER_OSPEEDR11_0 | GPIO_OSPEEDER_OSPEEDR5_1 | GPIO_OSPEEDER_OSPEEDR5_0 | GPIO_OSPEEDER_OSPEEDR4_1 | GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR3_1 | GPIO_OSPEEDER_OSPEEDR3_0 | GPIO_OSPEEDER_OSPEEDR2_1 | GPIO_OSPEEDER_OSPEEDR2_0 | GPIO_OSPEEDER_OSPEEDR1_1 | GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR0_1 | GPIO_OSPEEDER_OSPEEDR0_0; GPIOF -> AFR[0] |= GPIO_AFRL_AFRL5_3 | GPIO_AFRL_AFRL5_2 | GPIO_AFRL_AFRL4_3 | GPIO_AFRL_AFRL4_2 | GPIO_AFRL_AFRL3_3 | GPIO_AFRL_AFRL3_2 | GPIO_AFRL_AFRL2_3 | GPIO_AFRL_AFRL2_2 | GPIO_AFRL_AFRL1_3 | GPIO_AFRL_AFRL1_2 | GPIO_AFRL_AFRL0_3 | GPIO_AFRL_AFRL0_2; GPIOF -> AFR[1] |= GPIO_AFRH_AFRH7_3 | GPIO_AFRH_AFRH7_2 | GPIO_AFRH_AFRH6_3 | GPIO_AFRH_AFRH6_2 | GPIO_AFRH_AFRH5_3 | GPIO_AFRH_AFRH5_2 | GPIO_AFRH_AFRH4_3 | GPIO_AFRH_AFRH4_2 | GPIO_AFRH_AFRH3_3 | GPIO_AFRH_AFRH3_2; /* PG0, PG1, PG4, PG5, PG8, PG15: AF PP + VHS + AF12 */ GPIOG -> MODER |= GPIO_MODER_MODER15_1 | GPIO_MODER_MODER8_1 | GPIO_MODER_MODER5_1 | GPIO_MODER_MODER4_1 | GPIO_MODER_MODER1_1 | GPIO_MODER_MODER0_1; GPIOG -> OSPEEDR |= GPIO_OSPEEDER_OSPEEDR15_1 | GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR8_1 | GPIO_OSPEEDER_OSPEEDR8_0 | GPIO_OSPEEDER_OSPEEDR5_1 | GPIO_OSPEEDER_OSPEEDR5_0 | GPIO_OSPEEDER_OSPEEDR4_1 | GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR1_1 | GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR0_1 | GPIO_OSPEEDER_OSPEEDR0_0; GPIOG -> AFR[0] |= GPIO_AFRL_AFRL5_3 | GPIO_AFRL_AFRL5_2 | GPIO_AFRL_AFRL4_3 | GPIO_AFRL_AFRL4_2 | GPIO_AFRL_AFRL1_3 | GPIO_AFRL_AFRL1_2 | GPIO_AFRL_AFRL0_3 | GPIO_AFRL_AFRL0_2; GPIOG -> AFR[1] |= GPIO_AFRH_AFRH7_3 | GPIO_AFRH_AFRH7_2 | GPIO_AFRH_AFRH0_3 | GPIO_AFRH_AFRH0_2; /* PH3: AF PP + VHS + AF12 */ GPIOH -> MODER |= GPIO_MODER_MODER3_1; GPIOH -> OSPEEDR |= GPIO_OSPEEDER_OSPEEDR3_1 | GPIO_OSPEEDER_OSPEEDR3_0; GPIOH -> AFR[0] |= GPIO_AFRL_AFRL3_3 | GPIO_AFRL_AFRL3_2; }